The present disclosures relates to a Complementary Metal Oxide Semiconductor (CMOS) image sensor.
In general, an image sensor is a semiconductor device converting an optical image into an electrical signal. There is a complementary MOS (CMOS) image sensor adopting a switching manner, using a predetermined number of MOS transistors per unit pixel and sequentially detecting outputs using thereof, which is manufactured using CMOS fabrication techniques. Alternatively, another type of image sensor is a charge coupled device (CCD) where metal-oxide-silicon (MOS) capacitors are located very closer to each other and a charge carrier is stored and transferred in the capacitor, a control circuit, and a signal processing circuit as a peripheral circuit.
The CMOS image sensor, which can convert the optical information of a subject into electrical signals, is constituted by signal processing circuitry including photodiodes, an amplifier, an A/D converter, an internal voltage generator, a timing generator, digital logic, etc. Such circuitry can be included in one chip, having great advantages of reduction of space, power, and costs.
Meanwhile, the CMOS image sensor can be classified as a 3T type, a 4T type, and a 5T type, etc., according to the number of transistors per unit pixel. The 3T type is constituted by one photodiode and three transistors per unit pixel, and the 4T type is constituted by one photodiode and four transistors per unit pixel, etc.
Herein, an exemplary circuit and layout for the unit pixel of a 4T type CMOS image sensor will be described.
FIG. 1 is an equivalent circuit view of a 4T type CMOS image sensor of the related art, and FIG. 2 is a layout showing a unit pixel of a 4T type CMOS image sensor of the related art.
As shown in FIGS. 1 and 2, a unit pixel 100 of a CMOS image sensor comprises a photodiode 10 as a photoelectric converter and four transistors. The four transistors are a transfer transistor 20, a reset transistor 30, a drive transistor 40, and a select transistor 50, respectively. A load transistor 60 may be electrically connected to the output terminal OUT of the respective unit pixels 100.
A device isolating layer is formed on a semiconductor substrate by means of a STI (Shallow Trench Isolation) or LOCOS process defining an active area, wherein the active area includes the active areas of the four transistors. Herein, FD represents a floating diffusion area, Tx represents the gate of the transfer transistor 20, Rx represents the gate of the reset transistor 30, Dx represents the gate of the drive transistor 40, and Sx represents the gate of the select transistor 50.
In the unit pixel PX of the general 4T type CMOS image sensor, an active area is defined by forming a device isolating layer (not shown) in a portion of the substrate other than the active area, as shown in FIG. 2.
One photodiode PD is formed in a portion of the active area having a relatively wide width, and the gate electrodes 23, 33, 43, and 53 of the four transistors are formed in another portion of the active area. In other words, a transfer transistor 20 is formed using the gate electrode 23, a reset transistor 30 is formed using the gate electrode 33, a drive transistor 40 is formed using the gate electrode 43, and a select transistor 50 is formed using the gate electrode 53. Herein, the active areas of the respective transistors (excluding the channel regions under the respective gate electrodes 23, 33, 43, and 53) are implanted with impurity ions so that source/drain (S/D) areas of the respective transistors are formed.
Specifically describing the device isolating layer, the device isolating layer may be formed by Local Oxidation of Silicon (LOCOS) in a CMOS image sensor where the minimum line width of a circuit is 0.35 μm or more. However, the device isolating layer may be formed by STI (Shallow Trench Isolation), which is advantageous in a high-integration of a device, in a CMOS image sensor where the minimum line width is 0.25 μm 0.18 μm, or less.
When forming the device isolating layer in such a STI manner, in a boundary portion A of a photodiode adjacent to the device isolating layer, dislocation in the silicon lattice frequently occurs due to damage during the etching process for forming a trench structure. Such a dislocation portion A in a silicon lattice structure may serve as an electron trap, capturing electrons so that it can deteriorate low-light level characteristics of the CMOS image sensor. In other words, since the light quantity incident to the photodiode is small in a low-light level environment, the amount of charge to be subject to photoelectric conversion in the photodiode should be correspondingly small. However, it is believe that electrons captured in the electron traps described above may reproduce an image by passing through the transfer transistor 16 so that the characteristics of the image sensor deteriorates in a low-light level environment.